The embodiments of present invention relate to a thin film transistor liquid crystal display (TFT-LCD), particularly to an array substrate of thin film transistor liquid crystal display and the method of manufacturing the same.
TFT-LCD plays a dominant role in current flat screen display market, due to its excellent characteristics such as small volume, low power consumption and free of radiation. For TFT-LCD, array substrate and the manufacture process thereof significantly affect the performance, yield and price of a display product.
In order to effectively lower the price of TFT-LCD and improve product yield, the manufacture process of TFT-LCD array substrate becomes more and more simplified, from an original 7 masks process to current 4 masks process based on slit photolithographic technology.
In a conventional 4 masks process, a gray or halftone mask is used to complete the manufacture of an active layer, data lines, source electrodes, drain electrodes and TFT channel regions in a single patterning process. The process is described in more detail as following. Firstly, gate lines and gate electrodes are formed in a first patterning process. Then, a gate insulation layer, a semiconductor layer, a doped semiconductor layer (ohmic contact layer) and a source drain metal layer are subsequently deposited on a substrate having the gate lines and gate electrodes formed thereon. Next, data lines, an active layer, source drain electrodes and TFT channel regions are patterned with a gray or halftone mask through wet etching and a multi-steps etching process (etching the semiconductor layer→ashing→dry etching→etching the doped semiconductor layer) in a second patterning process using slit photolithograph. Next, a passivation layer is deposited and patterned to form through holes therein in a third patterning process. Finally, a transparent conductive layer is deposited and patterned into pixel electrodes in a fourth patterning process.
In the above conventional method, in order to completely remove the ohmic contact layer at the TFT channel region by dry etching while satisfying the requirement for the uniformity of the deposited film and the uniformity of etching, it is often necessary to perform over etching so as to remove a part of the underlying semiconductor layers. Thus, the semiconductor layer must be made thicker with a thickness of 100-300 nm. The off-state current of the TFT can be calculated as following:
            I      off        =                  q        ⁡                  (                                    n              ⁢                                                          ⁢                              μ                e                                      +                          p              ⁢                                                          ⁢                              μ                p                                              )                    ⁢              Wds        L            ⁢              V        ds              ,in which q is electron charge, n is electron density, p is hole density, μe is electron mobility, μp is hole mobility, W is TFT channel width, L is TFT channel length, ds is thickness of the active layer at TFT channel and Vds is potential difference between the source electrode and the drain electrode. According to the above equation, the off-state current of the TFT increases as the thickness of the active layer increases, thus reducing the retention time of the charge at the pixel electrode and directly affecting the performance of the TFT. Moreover, the contact resistance between the ohmic contact layer and the TFT channel increases with thicker active semiconductor layer, and thus decreasing the conductivity.